1. Field
This disclosure generally relates to cache memory, such as, a cache memory to support a low power mode of operation.
2. Background Information
As is well known, a cache or cache memory stores information, such as for a computer or computing system. The performance of a cache tends to decrease data retrieval times for a processor. The main memory forwards specific subsets of data to be stored into the cache memory. A few examples of data include instructions and addresses. Typically, at least one cache line within the cache memory is updated with new data, commonly referred to as a “dirty line or modified”. In contrast, a clean line of a cache has data that has not changed with respect to main memory. Eventually, the new data for the dirty line or lines is written back into main memory to insure coherency between the cache memory and main memory.
Cache memories have a range of different architectures with respect to addresses locations mapped to predetermined cache locations. For example, cache memories may be direct mapped or fully associative. Alternatively, another cache memory is a set associative cache, which is a compromise between a direct mapped cache and fully associative cache. In a direct mapped cache, there is one address location in each set. Conversely, a fully associative cache that is N-way associative has a total number of N blocks in the cache. Finally, a set associative cache, commonly referred to as N-way set associative, divides the cache into a plurality of N ways wherein each address is searched associatively for a tag address.
The demand for more powerful computers and communication products has resulted in faster processors that often have higher die temperatures and consume increasing amounts of power. However, design engineers struggle with reducing power consumption and die temperature. For example, a cache needs to insure synchronization of data with main memory and to support a processor's low power mode of operation, such as, an idle state to utilize a low level of power. However, every way of a typical cache memory needs to receive power until the dirty lines have been written back to main memory. A flush operation initiates writing the dirty lines back to the main memory. Thus, every way of a typical cache memory needs to receive power until a flush operation has completed. Therefore, a typical cache memory cannot support a processor that is idle for an intermittent time during a low power mode of operation. Furthermore, a typical cache memory can support a processor that is idle for an extended amount of time only after completion of a flush operation.